Name
Company
| Email
Phone
|
|
Schematic Diagram:
|
1. Design Software:
|
Altium
Designer Eagle 5.6
|
|
2. Will
HyTek-ED need to create your schematic?
|
Yes
No
|
If
yes: Does HyTek-ED have all data sheets for your parts?
|
Yes
No
|
|
3. Do
you have a Nets List from your schematic?
|
Yes
No
|
|
| 4. What
format is the Nets List in? |
|
|
| 5. Enter
number of nets. |
|
|
| 6. Enter
number of components. |
|
|
| 7. Do
you have a final Bill Of Materials for your design? |
Yes
No
|
|
|
8. Are
all parts fully defined? |
Yes
No
|
|
(PN, Vendor PN, Description, Reference Designator) |
|
| 9. Do
you have component libraries? |
Yes
No
|
|
| 10. Would
you like Signal Integrity and Simulation Analaysis? |
Yes
No
|
|
| 11. Do
you need FPGA Software Design? |
Yes
No
|
|
| 12. Enter
type of FPGA used. |
|
|
13.
Type of design:
|
|
Board Outline:
|
1. Do
you have a mechanical drawing of the Board Outline?
|
Yes
No
|
|
2. Is
the board outline in Electronic Format?
|
Yes
No
|
|
3. Are
all connector mounting locations defined?
|
Yes
No
|
|
4. Are
all trace and component keep-out areas defined?
|
Yes
No
|
|
5. Are
mounting holes connected to ground?
|
Yes
No |
Connector mounting holes connected to ground?
|
Yes
No
|
|
6. What
are the silkscreen marking requirements?
|
Top
Silkscreen Only
Enter any
special Requirements for Silkscreen/Soldermask Color
|
|
PCB Design Database:
|
1. Board
should be designed in what type of software?
|
Altium
Designer Eagle 5.6
|
|
2. Do
you require Fabrication and Assembly Drawings?
|
Yes
No
|
|
3. Do
you have sample drawings of your Fab and Assy?
|
Yes
No
|
|
4. Do
you require a company logo on PCB
|
Yes
No
|
|
5. Do
you have your company formats on DXF or other
CAD Database? |
Yes
No
|
|
6. Do
you have a preferred set of Fabrication Drawing Notes?
|
Yes
No |
|
7. Do
you require re-numbering for Reference Designations?
|
Yes
No
|
If
Yes:
Pattern Style (left-right, Top-Bottom,
etc.) |
|
|
8.
Special components or circuitry:
(Use Ctrl key to multi-select items)
|
Total
special components count?
(How many BGA's, etc...)
|
|
Placement:
|
| 1. Do
you have a pre-placement sketch |
Yes
No |
|
2. Are
there special requirements for placement? Such as height, thermal, spacing, clock length?
|
|
|
3. Are
there components on both sides of the board?
|
Yes
No
|
|
4. Are
the "sources and termination's" defined on the schematic
for Terminating Resistors? |
Yes
No
|
|
| 5. Which,
if any, components require sockets? |
|
|
| 6. What
size plots would you like for the Placement Review? |
|
|
Routing:
|
1. Do
you have a list of your critical nets?
|
Yes
No
|
|
| 2. Describe
any special concerns for critical nets. |
|
|
3. What
is your desired Layer Stack-up?
|
Ex. top,pwr1,sig1,sig1,gnd1,bot
|
|
4. What
is the desired Via size?
|
hole |
pad
|
|
5.
Special routing on PCB:
(Use Ctrl key to multi-select items)
|
|
|
| 6. What
are the minimal trace size and spacing?
If you have a design rules file, upload it at the end of this form
instead.
|
Trace
Size
|
|
Via
to Via
|
|
Via
to Pad
|
|
Via
to Signal
|
|
Signal
to Signal
|
|
Signal
to Pad
|
|
Pad
to Pad
|
|
Copper
pour clearance
|
|
|
Panelization and Test
|
1. Is
a Panel Drawing Required?
|
Yes
No
|
|
2. Do
you require the Gerber data in Panelized format?
|
Yes
No
|
|
3. Do
you require a test point on every signal?
|
Yes
No
|
|
4. Should
a DFT review be performed on the input schematic?
|
Yes
No
|
|
5. What
size and spacing is required for the test points?
|
|
|
Deliverables:
|
1. Please check off the required deliverables:
|
A. Project Database.
|
B. Gerber / Drill
/ ODB++ Data.
|
C. PCB
/ Schematic Libraries.
|
D. Smart
PDF Schematic
|
E. Signal
Integrity / Simulation Models.
|
F. ATE (Auto test data)
files & AIS (Auto Insertion data) files
|
G. DFT
/ DFM Results.
|
H. DXF/DWG
of Assembly Drawing on Disk
|
I. DXF/DWG
of Fabrication Drawing on Disk
|
J. DXF/DWG
of Panel Drawing on Disk
|
|
|
K. Pen
plots of:
|
Artwork
|
Assembly Drawing
|
Fabrication Drawing
|
Panel Drawing
|
L. PCB
Bare Board and Assembly Quote
|
|
|
M. Other:
|
Upload any Netlists, BOM, Design Rules, or other quote related files as a
.zip file if available.